Autem vel eum iriure dolor in hendrerit in vulputate velit esse molestie consequat, vel illum dolore eu feugiat nulla facilisis at vero eros et dolore feugait.
–prune delete refs that no longer exist on the remote. 如果远端服务器已经删除了某个分支，在 repo sync 时加上 --prune 选项，可以让本地仓库删除对这个分支的跟踪引用。查看 repo 的 .repo/repo/project.py 源码，这个选项实际上是作为 git fetch 命令的选项来执行。查看 man git-fetch 对自身 --prune 选项的说明如下，可供参考：-p, –prune After fetching, remove any remote-tracking references that no longer exist on the remote.
[root@XiaoLong /]# date -s "2018-07-28 14:21:22" //设置全部日期与时间
[root@XiaoLong /]# date -s "14:30:22" //只设置时间
[root@XiaoLong /]# date -s "2017-07-28" //设置日期，时间默认为00:00:00
格式示例
[root@XiaoLong /]# date -r app // -r选项可以打印出指定文件的最后修改时间
Fri Apr 29 05:17:34 UTC 2016
[root@XiaoLong /]# date -d 23:39:00 //打印出指定格式时间（只是打印效果没有其他效果）
Sat Apr 30 23:39:00 UTC 2016
[root@XiaoLong /]# date -s 12:20:30 //设置系统时间为12点20分30秒
Sat Apr 30 12:20:30 UTC 2016
[root@XiaoLong /]# date -s 2016.04.30-23:20:10 //设置系统时间为2016年4月30日23点20分10秒
Sat Apr 30 23:20:10 UTC 2016
struct rtc_time {
int tm_sec; //秒
int tm_min; //分钟
int tm_hour; //小时
int tm_mday; //天
int tm_mon; //月
int tm_year; //年
int tm_wday; //一周中的某一天
int tm_yday; //一年中的某一天
int tm_isdst; //夏令时有效
};
/* DDR model number: MT40A1G16KNR-062E:E */
#ifdef CONFIG_SYS_DDR_RAW_TIMING
dimm_params_t ddr_raw_timing = {
.n_ranks = 1, /* Number of ranks/ chip selects of DDR */
.rank_density = 8589934592u, /* this is size in one rank, here 8GB */
.capacity = 8589934592u, /* this is the total size, here 8GB */
.primary_sdram_width = 64, /* this is the data bus width */
.ec_sdram_width = 8, /* this is the ECC data width */
.die_density = 0x5, /* this is each DRAM die density, here twin 8Gbit die density. 0x44Gbit, 0x58Gbit, 0x616Gbit*/
.registered_dimm = 0, /* if register chip is used similar to an RDIMM = 1, otherwise = 0 */
.mirrored_dimm = 0, /* =1 if C/A bus mirroring is used, all UDIMMs with two ranks are mirrored */
.n_row_addr = 16, /* number of rows from dram datasheet */
.n_col_addr = 10, /* number of columns from dram datasheet */
.bank_addr_bits = 0, /* for DDR4 this is always = 0 defining two bits bank address in DRAM */
.bank_group_bits = 2, /* for x16 dram = 1, 1-bit BG, for x8 dram = 2, 2-bits for BG */
.edc_config = 2, /* leave as is, does not change. 0no ECC, 2 ECC*/
.burst_lengths_bitmask = 0x0c, /* leave as is, this is needed for uboot masking, does not change */
.tckmin_x_ps = 625, /* tck min = 625ps from DRAM datasheet */
.tckmax_ps = 1500, /* tck max = 1500ps from DRAM datasheet */
.caslat_x = 0x00FFFA00, /* leave as is, this is needed for uboot masking, does not change */
.taa_ps = 13750, /* tAA from DRAM datasheet (ps)*/
.trcd_ps = 13750, /* tRCD from DRAM datasheet (ps) */
.trp_ps = 13750, /* tRP from DRAM datasheet (ps)*/
.tras_ps = 32000, /* tRAS from DRAM datasheet (ps) */
.trc_ps = 45750, /* tRC = tRP+tRCD or from DRAM datasheet (ps)*/
.trfc1_ps = 350000, /* tRFC1 from DRAM datasheet (ps)*/
.trfc2_ps = 260000, /* tRFC2 from DRAM datasheet (ps)*/
.trfc4_ps = 160000, /* tRFC4 from DRAM datasheet (ps)*/
.tfaw_ps = 21000, /* tFAW from DRAM datasheet (ps)*/
.trrds_ps = 2500, /* tRRD_S from DRAM datasheet (ps)*/
.trrdl_ps = 4900, /* tRRD_L from DRAM datasheet (ps)*/
.tccdl_ps = 5000, /* tCCD_L from DRAM datasheet (ps)*/
.refresh_rate_ps = 7800000, /* tREFI from DRAM datasheet (ps)*/
};
1588 setting following information:
*******************************************
1) For the constant pulse width of the PPS signal, you must set the Fiper value that satisfies the equation given in LS1046ADPAARM (page 1254).
2) To get a pulse at every 1 second, the value written in Fiper register + TMR_CTRL[TCLK_PERIOD] must equal 1000,000,000.
e.g. given the two examples of different pulse width:
Case 1:
-Clock_IN = 125MHz
-Nominal_clock = 100MHz
-Frequency Div Ratio = Clock_IN/Nominal_clock = 125/100 = 1.25
-Addenden = (2^32)/1.25 = 3,435,973,836 = 0xCCCCCCCC
-TCLK_PERIOD should be equal to reciprocal of frequency of “nominal clock” and is recommended to have TCLK_PERIOD as integral factor of 10^9 = 10^9 / Nominal clock = 10^9 / 100*10^6 = 10 = 0xA
-Prescalar = 1000
-Output_Clock = 100MHz/1000 = 0.1MHz = 100KHz
-Fiper value = tmr_prsc * tclk_period * N - tclk_period, where N is an integer more than 2
= 1000 * 10 * 100000 - 10
= 999,999,990
= 0x3B9AC9F6
In this case, you will see pulse with width of 1/100KHz = 0.01 ms every 1 second
Case 2:
-Clock_IN = 125MHz
-Nominal_clock = 100MHz
-Frequency Div Ratio = Clock_IN/Nominal_clock = 125/100 = 1.25
-Addenden = (2^32)/1.25 = 3,435,973,836 = 0xCCCCCCCC
-TCLK_PERIOD should be equal to reciprocal of frequency of “nominal clock” and is recommended to have TCLK_PERIOD as integral factor of 10^9 = 10^9 / Nominal clock = 10^9 / 100*10^6 = 10 = 0xA
-Prescalar = 10000
-Output_Clock = 100MHz/10000 = 0.01MHz = 10KHz
-Fiper value = tmr_prsc * tclk_period * N - tclk_period, where N is an integer more than 2
= 10000 * 10 * 10000 - 10
= 999,999,990
= 0x3B9AC9F6
In this case, you will see pulse with width of 1/10KHz = 0.1 ms every 1 second
-examples: dpaa2
TimerOsc = 125 MHz
tclk_period = 10 nanoseconds
NominalFreq = 1000 / 10 = 100 MHz
FreqDivRatio = TimerOsc / NominalFreq = 125 / 100 = 1.25 (must be greater that 1.0)
tmr_add = ceil(2^32 / FreqDivRatio) = ceil(2^32 / 1.25) = 3,435,973,837 = 0xcccccccd
OutputClock = NominalFreq / tmr_prsc = 100 / 10000 = 0.01 MHz
PulseWidth = 1 / OutputClock = 1 / 0.01= 100 microseconds (attention:The 1pps pulse width is related to the 1588 output clock frequency.)
FiperFreq1 = desired frequency in Hz = 1 Hz
FiperDiv1 = 1000000 * OutputClock / FiperFreq1 = 1000000 * 0.01 / 1 = 10000
(1) tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period = 10000 * 10 * 10000 - 10 = 999,999,990
FiperFreq2 = desired frequency in Hz = 100 Hz
FiperDiv2 = 1000000 * OutputClock / FiperFreq2 = 1000000 * 0.01 / 100 = 100
tmr_fiper2 = tmr_prsc * tclk_period * FiperDiv2 - tclk_period = 10000 * 10 * 100 - 10 = 9,999,990
max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1 = 1000000000 * (1.25 - 1.0) - 1 = 249,999,999
soc {
ptp-timer@8b95000 {
compatible = "fsl,dpaa2-ptp";
reg = <0x0 0x8b95000 0x0 0x100>;
clocks = <&clockgen 4 1>;
little-endian;
fsl,extts-fifo;
fsl,cksel = <0>;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <10000>;
fsl,tmr-add = <0xcccccccd>;
fsl,tmr-fiper1 = <999999990>;
fsl,tmr-fiper2 = <9999990>;
fsl,tmr-fiper3 = <499990>;
fsl,max-adj = <249999999>;
};
};
more info: 8.7.7.4 PTP device tree node configuration LSDK user guide 2108 or ref dts in kernel
:vim ./Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
* Freescale QorIQ 1588 timer based PTP clock
General Properties:
- compatible Should be "fsl,etsec-ptp" for eTSEC
Should be "fsl,fman-ptp-timer" for DPAA FMan
Should be "fsl,dpaa2-ptp" for DPAA2
Should be "fsl,enetc-ptp" for ENETC
- reg Offset and length of the register set for the device
- interrupts There should be at least two interrupts. Some devices
have as many as four PTP related interrupts.
Clock Properties:
- fsl,cksel Timer reference clock source.
- fsl,tclk-period Timer reference clock period in nanoseconds.
- fsl,tmr-prsc Prescaler, divides the output clock.
- fsl,tmr-add Frequency compensation value.
- fsl,tmr-fiper1 Fixed interval period pulse generator.
- fsl,tmr-fiper2 Fixed interval period pulse generator.
- fsl,tmr-fiper3 Fixed interval period pulse generator.
Supported only on DPAA2 and ENETC hardware.
- fsl,max-adj Maximum frequency adjustment in parts per billion.
- fsl,extts-fifo The presence of this property indicates hardware
support for the external trigger stamp FIFO.
- little-endian The presence of this property indicates the 1588 timer
IP block is little-endian mode. The default endian mode
is big-endian.
These properties set the operational parameters for the PTP
clock. You must choose these carefully for the clock to work right.
Here is how to figure good values:
TimerOsc = selected reference clock MHz
tclk_period = desired clock period nanoseconds
NominalFreq = 1000 / tclk_period MHz
FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
tmr_add = ceil(2^32 / FreqDivRatio)
OutputClock = NominalFreq / tmr_prsc MHz
PulseWidth = 1 / OutputClock microseconds
FiperFreq1 = desired frequency in Hz
FiperDiv1 = 1000000 * OutputClock / FiperFreq1
tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
driver expects that tmr_fiper1 will be correctly set to produce a 1
Pulse Per Second (PPS) signal, since this will be offered to the PPS
subsystem to synchronize the Linux clock.
Reference clock source is determined by the value, which is holded
in CKSEL bits in TMR_CTRL register. "fsl,cksel" property keeps the
value, which will be directly written in those bits, that is why,
according to reference manual, the next clock sources can be used:
For eTSEC,
<0> - external high precision timer reference clock (TSEC_TMR_CLK
input is used for this purpose);
<1> - eTSEC system clock;
<2> - eTSEC1 transmit clock;
<3> - RTC clock input.
For DPAA FMan,
<0> - external high precision timer reference clock (TMR_1588_CLK)
<1> - MAC system clock (1/2 FMan clock)
<2> - reserved
<3> - RTC clock oscillator
When this attribute is not used, the IEEE 1588 timer reference clock
will use the eTSEC system clock (for Gianfar) or the MAC system
clock (for DPAA).
Example:
ptp_clock@24e00 {
compatible = "fsl,etsec-ptp";
reg = <0x24E00 0xB0>;
interrupts = <12 0x8 13 0x8>;
interrupt-parent = < &ipic >;
fsl,cksel = <1>;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <100>;
fsl,tmr-add = <0x999999A4>;
fsl,tmr-fiper1 = <0x3B9AC9F6>;
fsl,tmr-fiper2 = <0x00018696>;
fsl,max-adj = <659999998>;
};
ls1046可以编辑 vim ./arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
130 ptp_timer0: ptp-timer@1afe000 {
131 compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
132 reg = <0x0 0x1afe000 0x0 0x1000>;
133 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clockgen 3 0>;
135 fsl,extts-fifo;
136 };
增加属性根据需求：
cksel --- 时钟选择。参考上文。
tclk-period --- 想获取周期，即一个cnt对应周期 单位ns，决定了1588的 nominalfreq，nominalfreq= 1000/tclk-period
+ fsl,cksel = <0>; /* 125M external high precision timer reference clock,rdb board */
+ fsl,tclk-period = <10>; /* 10 ns nominalfreq = 1000/10 = 100MHz */
+ fsl,tmr-prsc = <10000>; /* 输入时钟100MHz 输出时钟= 100/tmr-prsc=1/100Mhz=10Khz,且决定了1pps的脉宽是1/10Khz=0.1ms.
+ fsl,tmr-add = <0xCCCCCCCD>; /* ceil(2^32/FreqDivRatio)=(4294967296/(125M/100M)) = 0xCCCCCCCD
+ fsl,tmr-fiper1 = <999999990>; /* tmr_prsc * tclk_period * FiperDiv1 - tclk_period = 10000*10*(10*1000Hz/1Hz)-10 = 999,999,990 = 0x3B9AC9F6
+ fsl,tmr-fiper2 = <9999990>; /* FiperFreq2 = desired frequency in Hz = 100 Hz;FiperDiv2 = 1000000 * OutputClock / FiperFreq2 = 1000000 * 0.01 / 100 = 100;tmr_fiper2 = tmr_prsc * tclk_period * FiperDiv2 - tclk_period = 10000 * 10 * 100 - 10 = 9,999,990
+ fsl,max-adj = <>; /* 10^9 *(FreqDivRatio - 1.0)-1 = 1000000000 * (FreqDivRatio - 1.0) - 1 = 1000000000 * (1.25 - 1.0) - 1 = 249,999,999
-fsl，cksel定时器参考时钟源。
-fsl，tclk period Timer参考时钟周期（纳秒）。
-fsl、tmr prsc预分频器对输出时钟进行分频。
-fsl、tmr增加频率补偿值。
-fsl，tmr-fiper1固定间隔周期脉冲发生器。
-fsl，tmr-fiper2固定间隔周期脉冲发生器。
-fsl，tmr-fiper3固定间隔周期脉冲发生器。
仅在DPAA2和ENEC硬件上受支持。
-fsl，max adj最大频率调整，单位为十亿分之一。
-fsl，extts fifo此属性的存在表示硬件支持外部触发戳FIFO。
-little endian此属性的存在表示1588计时器
IP块为小端模式。默认endian模式是big endian。
I guess you have already installed SCTP, if so, you are probably missing the nf_conntrack_proto_sctp module. This module is required for iptables to work with SCTP. Try this:
