/* DDR model number: MT40A1G16KNR-062E:E */
#ifdef CONFIG_SYS_DDR_RAW_TIMING
dimm_params_t ddr_raw_timing = {
     .n_ranks = 1, /* Number of ranks/ chip selects of DDR */
     .rank_density = 8589934592u, /* this is size in one rank, here 8GB */
     .capacity = 8589934592u, /* this is the total size, here 8GB */
     .primary_sdram_width = 64, /* this is the data bus width */
     .ec_sdram_width = 8, /* this is the ECC data width */
     .die_density = 0x5, /* this is each DRAM die density, here twin 8Gbit die density. 0x44Gbit, 0x58Gbit, 0x616Gbit*/
     .registered_dimm = 0, /* if register chip is used similar to an RDIMM = 1, otherwise = 0 */
     .mirrored_dimm = 0, /* =1 if C/A bus mirroring is used, all UDIMMs with two ranks are mirrored */
     .n_row_addr = 16, /* number of rows from dram datasheet */
     .n_col_addr = 10, /* number of columns from dram datasheet */
     .bank_addr_bits = 0, /* for DDR4 this is always = 0 defining two bits bank address in DRAM */
     .bank_group_bits = 2, /* for x16 dram = 1, 1-bit BG, for x8 dram = 2, 2-bits for BG */
     .edc_config = 2, /* leave as is, does not change. 0no ECC, 2 ECC*/
     .burst_lengths_bitmask = 0x0c, /* leave as is, this is needed for uboot masking, does not change */
     .tckmin_x_ps = 625, /* tck min = 625ps from DRAM datasheet */
     .tckmax_ps = 1500, /* tck max = 1500ps from DRAM datasheet */
     .caslat_x = 0x00FFFA00, /* leave as is, this is needed for uboot masking, does not change */
     .taa_ps = 13750, /* tAA from DRAM datasheet (ps)*/
     .trcd_ps = 13750, /* tRCD from DRAM datasheet (ps) */
     .trp_ps = 13750, /* tRP from DRAM datasheet (ps)*/
     .tras_ps = 32000, /* tRAS from DRAM datasheet (ps) */
     .trc_ps = 45750, /* tRC = tRP+tRCD or from DRAM datasheet (ps)*/
     .trfc1_ps = 350000, /* tRFC1 from DRAM datasheet (ps)*/
     .trfc2_ps = 260000, /* tRFC2 from DRAM datasheet (ps)*/
     .trfc4_ps = 160000, /* tRFC4 from DRAM datasheet (ps)*/
     .tfaw_ps = 21000, /* tFAW from DRAM datasheet (ps)*/
     .trrds_ps = 2500, /* tRRD_S from DRAM datasheet (ps)*/
     .trrdl_ps = 4900, /* tRRD_L from DRAM datasheet (ps)*/
     .tccdl_ps = 5000, /* tCCD_L from DRAM datasheet (ps)*/
     .refresh_rate_ps = 7800000, /* tREFI from DRAM datasheet (ps)*/

};